A programmable logic device (PLD) generally includes at least one memory, which may be located external to or embedded in the PLD. When the memory is located external to the PLD, the PLD is provided with an external memory interface bus that can be used for communicating with the external memory. The data are transmitted to/from the PLD from/to the external memory via the external memory interface bus. During transmission, bits in the data might be switching states. When a large number of bits in the data simultaneously switch states, this can result in noise. The effect of simultaneous switching states is commonly referred to as a simultaneous switching output (SSO) effect. The noise generated by the SSO effect can cause signal integrity problems thereby causing corruption of data. Additionally, the error detection schemes used in digital circuits generally do not provide any means for detecting the errors, which may occur to bits in the data that indicate such process as encoding.
Accordingly, there exists a need for a system and a method for a PLD with an external memory that minimizes SSO effect. Also, there exists a need to detect errors that may occur to bits in the data that indicate such process as encoding.